CW01 features ? low phase noise ? 100v open drain n-channel ? high speed d fip-fop ? high speed mosfet gate driver ? up to 200mhz clock input ? v dd and v ll undervoltage lockout applications ? diagnostic medical ultrasound ? fluid fow measurement general description the supertex CW01 is a four-channel, low phase noise, continuous wave transmit ic. a high speed d fip-fop is provided to allow the d in frequency to be aligned to a high frequency clock. the output n-channel is turned on when a logic high is clocked into the d fip-fop. data are clocked in during the low to high transition. vd1, vd2, vd3 and vd4 are four individual input supply voltages for the n-channel output mosfet gate drivers. high peak currents are drawn from these gate drives when the output mosfets are switching. to minimize jitter caused by voltage ripples, each channel has its own gate drive voltage pin; vd1, vd2, vd3 and vd4. a series ferrite bead and a decoupling capacitor are recommended on each vdx pin to minimize output jitter and channel to channel crosstalk. both v dd and v ll have undervoltage lockout to prevent spurious turn-on. typical application circuit four-channel, low phase noise, low power, continuous wave transmitter hv out 1 pgnd1 translator and driver v d1 v ll 270 h 0.1f 0.1f 5.0v 2.5v 2.0 to 5.0mhz 96mhz vd1 vdd oe vll d in 1 clk vss d in 1 q1 clk bav99 tx pzt 8.0v bav23 (one of four channels) supertex inc. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
2 CW01 ordering information device package option 24-lead qfn 4.00x5.00mm body 1.00mm height (max) 0.50mm pitch CW01 CW01k6-g -g indicates package is rohs compliant (green) absolute maximum ratings parameter value v ll , logic supply -0.3 to +6.0v v dd , level translator voltage -0.5 to +6.0v v dx , gate drive voltage -0.5 to +6.0v hv out , high voltage output drain voltage -0.5 to 120v maximum junction temperature +125c storage temperature range -65c to +150c power dissipation, t a = 25c 3.0w 1 ja 26.9c/w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. note: 1. device mounted on a 4 layer 3 by 4 board. pin confguration 24-lead qfn (k6) (top view) product marking 24-lead qfn (k6) oe vss vd1 vd2 pgnd1 hv out 1 pgnd2 hv out 2 vss hv out 3 pgnd3 hv out 4 din4 vll vss vd4 vd3 pgnd4 din1 din2 vdd clk vss din3 1 24 y = last digit of year sealed w = code for week sealed l = lot number = ?green? packaging CW01 ywll package may or may not include the following marks: si or supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
3 CW01 symbol parameter min typ max unit test conditions hv out high voltage output 0 - 100 v --- v dd v dd voltage range 4.5 5.0 5.5 v --- t vdd-on v dd rise time 50 - - s --- v ll v ll voltage range 1.65 2.5 5.5 v --- t vll-on v ll rise time 50 - - s --- v din logic input voltage range 0 - v ll v --- v dx gate drive voltage 4.5 5.0 5.5 v --- t vdx-on v dx rise time 50 - - s --- i ddq v dd quiescent current - 63 100 a --- i dd v dd average current - 23.5 30 ma f clk = 200mhz, f out = 5.0mhz, all 4-ch active i llq v ll quiescent current - 8.1 20 a --- i ll v ll average current - 380 600 a f clk = 200mhz, f out = 5.0mhz, all 4-ch active i dxq v dx quiescent current - 0 1.0 a --- i dx v dx average current - 11.3 30 ma f clk = 200mhz, f out = 5.0mhz, all 4-ch active v ih input logic high voltage 0.8v ll - v ll v --- v il input logic low voltage 0 - 0.2v ll v --- i ih input logic high current - - 1.0 a --- i il input logic high current -1.0 - - a --- r on output on resistance - 4.7 7.0 i in = 100ma i sat output saturation current - 0.8 - a v dd = hv out = 5.0v i hvleak high voltage output leakage - - 10 a hv out = 100v uvlo_v ll uvlo trip point for v ll - 1.5 - v --- uvlo_v dd uvlo trip point for v dd - 4.0 - v --- t j operating junction temperature -40 - +125 c --- dc electrical characteristics (v dd = v dx =5.0v, v ll = 2.5v, t j = 25oc unless otherwise specifed) supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
4 CW01 ac electrical characteristics (v dd = v dx =5.0v, v ll = 2.5v, t j = 25oc unless otherwise specifed) symbol parameter min typ max unit test conditions f clk clock frequency 0 - 200 mhz - t r , t f clock rise and fall times - 0.5 5.0 ns - t su set-up time, din to clk 2.0 - - ns - t h hold time, din from clk 1.0 - - ns - t hvf hv out fall time - 0.8 - ns load = 50 to 8.0v. see timing diagram t hvr hv out rise time - 3.3 - ns load = 50 to 8.0v. see timing diagram t dlh delay time from clk to hv out from low to high - 5.1 - ns load = 50 to 8.0v. see timing diagram t dhl delay time from clk to hv out from high to low - 2.6 - ns load = 50 to 8.0v. see timing diagram ?t dlhdelay delay time matching for t dlh - 0.5 1.0 ns - ?t dhldelay delay time matching for t dhl - 0.5 1.0 ns - t oe(on) output enable turn-on time - - 10 s t oe(off) output enable turn-off time - - 0.1 s - c out output capacitance - 8.0 - pf at 8.0v - 4.0 - pf at 100v phase noise phase noise - -171 -160 dbc db below carrier clk = 80mhz, d in = 2.0mhz freq offset = 1.0khz noise bandwidth = 140hz see test circuit. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
5 CW01 block diagram vdd vll oe d in 1 d in 2 d in 3 d in 4 clk vss v ll v ll v ll v ll v dd v dd v dd v dd v ll uvlo v dd uvlo d in 1 q1 clk d in 2 q1 clk d in 3 q1 clk d in 4 q1 clk vd1 hv out 1 pgnd1 vd2 hv out 2 pgnd2 vd3 hv out 3 pgnd3 vd4 hv out 4 pgnd4 sub timing diagram clk din hv out t dlh t hv r t hv f t dhl t h t su 50%5 0% 90% 90% 10 %1 0% 50%5 0% supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
6 CW01 test circuits ac timing phase noise hv out 1 pgnd1 hv out translator and driver v d1 v ll 0.1f 8.0v 0.1f 0.1f 5.0v 2.5v din clk vd1 vdd oe vll d in 1 clk vss d in 1 q1 clk 50 (one of four channels) hv out 1 (one of four channels) pgnd1 hv out translator and driver v d1 v ll 0.1f 50 50 0.1f 390 h 3.0v 0.1f 0.1f 5.0v 2.5v 2.0mhz 80mhz vd1 vdd oe vll d in 1 clk vss d in 1 q1 clk typical performance curve (test conditions: v ll = 2.5v, v dd = 5.0v, v d1 = v d2 = v d3 = v d4 = 5.0v, no load) i dd vs d in frequenc y 30 25 20 15 10 5 0 05 10 15 20 25 data in frequenc y (mhz ) i dd (ma) f clk = 200mhz f clk = 100mhz f clk = 50mhz supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
7 CW01 pin confguration and description pin # function description 1 d in 1 d fip-fop logic input for hv out 1. logic high will turn on output n-channel. 2 d in 2 d fip-fop logic input for hv out 2. logic high will turn on output n-channel. 3 vdd level translator supply. should be at the same potential as v dx . 4 clk logic clock input. 5 vss ground. should be externally shorted to all pgnd and vss pins. 6 d in 3 d fip-fop logic input for hv out 3. logic high will turn on output n-channel. 7 d in 4 d fip-fop logic input for hv out 4. logic high will turn on output n-channel. 8 vll logic input supply voltage. 9 vss ground. should be externally shorted to all pgnd and vss pins. 10 vd4 gate drive supply voltage for hv out 4. should be at the same potential as v dd . 11 vd3 gate drive supply voltage for hv out 3. should be at the same potential as v dd . 12 pgnd4 power ground for hv out 4. should be externally shorted to all pgnd and vss pins. 13 hv out 4 drain output for hv out 4. 14 pgnd3 power ground for hv out 3. should be externally shorted to all pgnd and vss pins. 15 hv out 3 drain output for hv out 3. 16 vss ground. should be externally shorted to all pgnd and vss pins. 17 hv out 2 drain output for hv out 2. 18 pgnd2 power ground for hv out 2. should be externally shorted to all pgnd and vss pins. 19 hv out 1 drain output for hv out 1. 20 pgnd1 power ground for hv out 1. should be externally shorted to all pgnd and vss pins. 21 vd2 gate drive supply voltage for hv out 2. should be at the same potential as v dd . 22 vd1 gate drive supply voltage for hv out 1. should be at the same potential as v dd . 23 vss ground. should be externally shorted to all pgnd and vss pins. 24 oe output enable logic input. logic low will turn all hv out off. center pad --- should be externally shorted to all pgnd and vss pins. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
8 (the package drawings in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) CW01 doc.# dsfp-CW01 a121511 24-lead qfn package outline (k6) 4.00x5.00mm body, 1.00mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 3.85* 2.50 4.85* 3.50 0.50 bsc ?0.30 0.00 0 o nom 0.90 0.02 0.25 4.00 2.65 5.00 3.65 0.40 - - max 1.00 0.05 0.30 4.15* 2.80 5.15* 3.80 ?0.50 0.15 14 o j edec registration mo-220, variation vghd-1, issue k, june 2006 * this dimension is not specifed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc.#: dspd-24qfnk64x5p050, version a101111. seating plane t op vi ew side v iew bottom v iew a a1 d e d2 b e2 a3 l l1 vi ew b vi ew b 1 note 3 note 2 note 1 (index area d/2 x e/2) 24 1 24 note 1 (index area d/2 x e/2) e notes: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?201 1 supertex inc. a ll rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
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